UNIT-II
1. A normalized floating-point decimal number is
a. 0.03456
b. 3.456
c. 34.56
d. 3456
2. The two parts in floating-point representation are
a. radix, mantissa
b. mantissa, base
c. mantissa , exponent
d. radix, exponent
3. The part in floating-point representation that denotes position of the radix point is
a. exponent
b. mantissa
c. base
d. both exponent and mantissa
4. In floating point representation, the fixed point mantissa
a. must be integer
b. may be integer
c. must be fraction
d. may be fraction or integer
5. In floating point representation, the fixed point mantissa
a. must be positive
b. may be positive
c. is signed number
d. must be negative
6. A normalized floating-point binary number is
a. 0.01010
b. 1010
c. 10.10
d. 1.010
7. Odd parity generator can be implemented with
a. AND function
b. OR function
c. exclusive & OR function
d. Exclusive - OR & Exclusive - Nor function
8. If 3 bit messages are transmitted suffixing with P (odd) bit the erroneous message is
a. 1011
b. 0111
c. 0010
d. 1010
9. Parity checker networks are constructed with logic circuits comprising
a. AND logic gates
b. OR logic gates
c. exclusive OR logic gates
d. NOR logic gates
10. Even parity generators can be implemented with
a. AND functions
b. OR functions
c. exclusive OR functions d. NOR functions
11. If 3 bit messages are transmitted suffixing with P (even) bit the erroneous message is
a. 0110
b. 1100
c. 0100
d. 1111
12. If a 3 bit message 010 is transmitted with suffix of even parity bit , the resultant
Message is
a. 0100
b. 0101
c. 1010
d. 0010
13. If a 3 bit message 101 is transmitted with suffix of even parity bit , the resultant
Message is
a. 1010
b. 1011
c. 0101
d. 1101
14. If a 3 bit message 110 is transmitted with suffix of odd parity bit , the resultant
Message is
a. 1100
b. 1101
c. 0110
d. 1110
15. If a 3 bit message 011 is transmitted with suffix of odd parity bit , the resultant
Message is
a. 0011
b. 1011
c. 0110
d. 0111
16. Even parity generator is constructed with logic circuits comprising
a. AND logic gates
b. OR logic gates
c. exclusive OR logic gates
d. NOR logic gates
17. A Common bus system is connected with four registers of 4-bit capacity using binary
MUXs . The number of MUXs required is
a. 4
b. 8
c. 3
d. 16
18. A Common bus system is connected with four registers of 4-bit capacity using binary
MUXs. The size of each MUX each is
a. 8 X 1
b. 4 X 1
c. 16 X 1
d. 12 X 1
19. The function that allows register transfer under a predetermined condition is
a. Conditional variable
b. Sample function
c. Control function
d. RTL function
20. The state of the three-state gate when input is not connected to output is
a. 0
b. 1
c. forbidden
d. high impedance state
21. Register transfer denoting memory write operation is
a. DA ←M {[AR]}
b. M {[AR]}←DR
c. M←DR
d. DR←M
22. The operation executed on data stored in registers is called
a. RTL instruction
b. Micro operation
c. Register logic
d. Nano operation
23. The symbolic notation used to describe the micro operation transfers among
registers is
called
a. Register Transfer language
b. Micro operations
c. Nano operation
d. Assembly language
24. The arithmetic micro operation R3←R1+ +1 denotes
a. The sum of R1 and R2 transferred to R3
b. The sum of 1's complement of R1 and R2
c. The sum of 2's complement of R1 and R2
d. Subtraction of R2 from R1
No comments:
Post a Comment