Tuesday, 12 November 2013

MP and MC interview Questions or viva Question , bits

 UNIT-3
1)._______ signal indicates the availability of valid data over address & data lines.
   a) DEN            b) INTR                   c) NMI                        d) READY                 [  a  ]
2). ______ clears the CWR.                                                                            [  b  ]
   a) READY               b) RESET        c) NMI                        d) TEST
3).MN/MX' = ______ for maximum mode of 8086.                                      [  a  ]
   a) 0               b) 1                  c) 2                  d) none
4)._____ is an edge triggered i/p which causes a Type 2 interrupt.                [  c  ]
   a) READY               b) RESET        c) NMI                        d) TEST
5). MN/MX' = ______ for minimum mode of 8086.                                      [  b  ]
   a) 0               b) 1                  c) 2                  d) none
6).How many processors are presented in minimum mode system.               [  a  ]
   a) 1               b) 2                  c) more than 1             d) none
7).Which of the following represents DMA controller.                                  [  c  ]
   a) 8253         b)8259             c) 8257            d) 8279
8).The function of the _____ is to store the address of starting memory to be
    Accessed by DMA channel.                                                                       [  b  ]
    a) TC  b) DMA address register   c) Mode set register  d) none
9)._____ i/p of 8086 causes processor to stop the current activity & start     [  d  ]
   execution from FFFF0H.                                                    
   a) CLK         b) ALE            c)READY       d) RESET                  
10).DMA  data transfer is the fastest among all the modes of data transfer.           
11).DMA stands for Direct Memory Access.
12).DMA data transfer is initiated only after receiving HLDA signal from CPU.
13).When read signal of 8086 is low , it indicates that the processor is performing
      Memory or I/O read operation.
14).The ALE o/p signal of 8086 indicates the valid address on address/data lines
      & is connected to latch enable i/p.
15). Access time is faster for
 a) ROM b) SRAM c) DRAM
16). In 8279 Strobed input mode, the control line goes low. The data on return lines is strobed in the .
a) FIFO byte by byte b) FILO byte by byte c) LIFO byte by byte d) LILO byte by byte.
17). ___ bit in ICW1 indicates whether the 8259A is cascade mode or not?
a) LTIM=0 b) LTIM=1 c) SNGL=0 d) SNGL=1
18).. In 8255, under the I/O mode of operation we have __ modes. Under which mode will have the following features
i) A 5 bit control port is available.
ii) Three I/O lines are available at Port C.
a) 3, Mode2 b) 2, Mode 2 c) 4, Mode 3 d) 3, Mode 2
19). In ADC 0808 if _______ pin high enables output.
a) EOC b) I/P0-I/P7 c) SOC d) OE
20). In 8279, a scanned sensor matrix mode, if a sensor changes its state, the ___ line goes ____ to interrupt the CPU.
a) CS, high b) A0, high c) IRQ, high d) STB, high
                                                UNIT -4
1)      Which of the following is programmable interrupt controller                        [  b  ]
a)      8253          b) 8259            c) 8255            d) 8279
2)      Which of the following is used as a keyboard/display controller                   [  d  ]
a)      8253          b) 8259            c) 8255            d) 8279
3)      The 8279 provides a max of ____ 7-segment display interface with CPU    [  a  ]
a)      16              b) 15                c) 8                  d) 12
4)      When 8255 is to be reset then which of these combinations are valid.          [  c  ]
a)      RD=0,WR=1,RESET=0,CS=0     b) RD=1,WR=0,RESET=0,CS=0
c).  RD=0,WR=1,RESET=1,CS=0     d) RD=0,WR=1,RESET=0,CS=1
      5)   A coil which attracts a rod to cause a mechanical displacement to operate   [  b  ]
            a mechanical leverage is called
a)      Solenoid      b) Actuator      c) Magnetizer            d) relay
6). _____ is the internal register of 8255.                                                             [  a  ]
     a) CWR            b) MSR           c) CMR           d) none
7)  There are _____ basic modes of operation of 8255.                                        [  c  ]
     a) 1          b) 3        c) 2             d) 6
8)  The MSB is ‘0’ for _____ mode of 8255.                                                       [  b  ]
     a) I/O                b) BSR                        c) minimum     d) Maximum
9)  Which of the following is basic I/O mode.                                                     [  c  ]
     a) BSR             b) mode-1        c) mode-0        d) mode-2
10) _____ is a device used to obtain an accurate position control of rotating shafts.
    a) stepper motor   b) ADC        c)DAC                        d) PPI                                      [  a  ]
11) A keyboard switches do not change position smoothly but generate transients.
     This is called key debounce.
12) In A/D converter ADC 0808 8  channels of analog input are available.
13) 8255 PPI contains ports.
14)Mode-2 mode of operation of 8255 is called strobed bidirectional I/O mode.
      15) The time taken by ADC from SOC to EOC signal is called Conversion delay.
      16) DAC stands for Digital to Analog converter.
      17) In stepper motor Stator is stationary.
      18) The modes of operation of 8279 are Input& output modes.
      19) PPI stands for Programmable Peripheral Interface.
      20) Define Interrupts?

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