UNIT-IV
1. If the content of 8 bit register R1 is 10001101. The content of register R1 after
Execution of R1←Cir R1 micro operation is
a. 11000110
b. 00011011
c. 01000110
d. 00011010
2. If the content of 8 bit register R1 is 11010011. The content of register R1 after
execution
of R1 ← ashr R1 micro operation is
a. 01101001
b. 10100110
c. 10100111
d. 11101001
3. The function denoted by arithmetic operation F=A-1 is
a. 1's complement
b. subtraction with borrow
c. 2's complement
d. decrement
4. The general-purpose computer register is
a. Data Register
b. Accumulator
c. Instruction register
d. Program counter
5. In direct addressing mode address part of instruction specifies
a. Address of next instruction
b. Address of register
c. Address of operand in memory
d. Operand itself
6. The computer register used to hold address of instruction is
a. Data Register
b. Accumulator
c. Instruction register
d. Program counter
7. The computer register that specifies memory address is
a. Address register
b. Accumulator
c. Instruction register
d. Temporary register
8. If it takes 5ns to read an instruction from memory, 2ns to decode the instruction, 3ns
To read the register file, 4ns to perform the computation required by the instruction, and
2ns to write the result into the register file, what is the maximum clock rate of the
processor?
a. 62.5 MHz
b. 20 MHz
c. 25 MHz
d. 6.25 MHz
9. The part of instruction code that specifies operation to be performed is
a. opcode
b. address
c. binary operand
d. the complete Instruction code
10. In IAS computer address part specifies
a. Address of next instruction
b. Address of register
c. Address of operand in memory
d. Operand itself
11. In indirect addressing mode address part of instruction specifies
a. Address of next instruction
b. Address of current instruction
c. Address of operand
d. Address of memory location containing address of operand
12. The computer register used to hold instruction code is
a. Data Register
b. Accumulator
c. Instruction register
d. Program counter
13. A computer uses a memory unit with 256K words of 32 bits each. A binary instruction
code is stored in one word of memory. The instruction has four parts: an indirect bit, an
operation code, a register code part to specify one of 64 registers, and an address part.
Draw the instruction word format and indicate the number of bits in each.
a. indirect 1bit, Opcode 5bits, Register 8bits, Address 18 bits
b. indirect 1bit, Opcode 15its, Register 8bits, Address 8 bits
c. indirect 1bit, Opcode 8bits, Register 8bits, Address 15 bits
d. indirect 1bit, Opcode 7bits, Register 9bits, Address 15 bits
14. The instruction that clears start stop flip flop and stops sequence counter from
Counting is
a. CLA b. INC c. SNE d. HLT
15. A computer uses a instruction format that has three parts: an indirect part, and
operationcode, and an address part. One of the operand is AC and is implicit. Another
operand isspecified in the address part. An instruction at 021 has I=0, an operation code
of the ANDinstruction, and an address part equal to 083 (all numbers are in hexadecimal)
containsthe operand B8 F2 and the content of AC is A937. Go over the instruction cycle
anddetermine the contents of the following registers at the end of the execute phase: PC,
AR,DR, AC, and IR.
a. 022, 083, B8F2, A832, 021
b. 021, 021, B8F2, A937, 021
c. 022, 022, A937, A832, 022
d. 021, 022, A937, B8F2,.021
16. Which of the following statement(s) is(are) correct?
a. CISC has more complex circuitry than RISC
b. CISC architectures tend to take more space in memory than the same programs
written for RISC architecture.
c. RISC architecture have more addressing modes than the CISC architecture.
d. RISC has more complex circuitry than RISC
17. A digital computer has a common bus system for 16 registers of 32 bits each. The
bus is constructed with multiplexers. How many selection inputs are there in each
multiplexer.
a. 4
b. 8
c. 16
d. 32
18. In the instruction cycle the phase that reads instruction into instruction register from
memory is
a. Fetch
b. Decode
c. Read effective address
d. execute the instruction
19. In the instruction cycle the phase that reads effective address from memory location
is
a. Fetch
b. Decode
c. Read effective address
d. execute the instruction
20. The instruction that increments accumulator is
a. CLA
b. INC
c. SNE
d. HLT
UNIT-V
1. The instruction that clears accumulator is
a. CLA
b. INC
c. SNE
d. HLT
2. The memory reference instruction that denotes operation M[AR]←M[AR]+1, if M[AR] +1=0 then PC←PC+1 is
a. AND
b. BSA
c. BUN
d. ISZ
3. The memory reference instruction that denotes operation M[AR]←PC,PC ←AR+1 is
a. AND
b. BSA
c. BUN
d. ISZ
4. The memory reference instruction that denotes operation PC ←AR is
a. AND
b. BSA
c. BUN
d. STA
5. The input-output instruction that denotes operation If (FGI =1) then PC←PC+1 is
a. INP
b. SKI
c. SKO
d. ION
6.The Input-Output Instruction that denotes operation If (FGO =1) then PC←PC+1 is
a. INP
b. SKI
c. SKO
d. ION
7.The memory reference instruction that denotes operation AC ← AC ∩ M[AR] is
a. AND
b. ADD
c. LDA
d. STA
8.The memory reference instruction that denotes operation M[AR]←AC is
a. AND
b. BSA
c. BUN
d. STA
9.The memory reference instruction that denotes operation AC ← M[AR] is
a. AND
b. BSA
c. BUN
d. LDA
10.In the process of information transfer to input register from input device the initial
Value of control flip-flop FGI is
a. 0(Zero)
b. 1 (one)
c. 2 (two)
d. 8 (eight)
11. In the process of information transfer to output register from accumulator the initial
value of control flip-flop FGO is
a. 0(Zero)
b. 1 (one)
c. 2 (two)
d. 8 (eight)
12.The CPU organization in which all operations are performed with an implied
Accumulator register is
a. General register Organization
b. Stack organization
c. Shared memory organization
d. Single accumulator organization
13.The CPU organization that does not use an address field for the instructions is
a. General register Organization
b. Stack organization
c. Shared memory organization
d. Single accumulator organization
14.The CPU organization in which all operations are performed with two or three
Register fields is
a. General register organization
b. Stack organization
c. Shared memory organization
d. Single accumulator organization
15.In Register Stack the stack pointer register (SP) contains
a. The word that is currently on top of stack
b. The address of the word that is currently on top of stack
c. The highest address of stack
d. The lowest address of stack
16.The addressing mode in which the address part of the instruction is added to
Program counter in order to obtain effective address is
a. Direct Address mode
b. Register Mode
c. Relative Address Mode
d. Register Indirect Mode
17.The DATA transfer instruction is
a. MOV
b. DEC
c. NEG
d. SUB B
18.The addressing mode in which the address part of the instruction gives effective
Address of operand is
a. Direct Address mode
b. Register Mode
c. Indirect Addressing Mode
d. Register Indirect Mode
19.The addressing mode in which the address part of the instruction gives address of
effective address of operand is
a. Direct Address mode
b. Register Mode
c. Indirect Address Mode
d. Register Indirect Mode
20.The DATA manipulation instruction is
a. MUL
b. LD
c. MOV
d. PUSH
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